SAK-XE167FM-72F80LAA Datasheet, PDF (134/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Electrical Parameters
4.6.7 Debug Interface Timing
The debugger can communicate with the XE167xM either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply; C_L= 20 pF.
Table 37 DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR 25¹⁾
t₁₂ SR 8
t₁₃ SR 8
t₁₄ SR −
t₁₅ SR −
t₁₆ SR 6
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns pad_type= stan
dard
DAP1 hold after DAP0 t₁₇ SR 6
−
−
ns pad_type= stan
rising edge
dard
DAP1 valid per DAP0
t₁₉ CC 17
20
−
clock period²⁾
ns pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t₁₁ ≥ t_SYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
134
V2.1, 2011-07