SAK-XE167FM-72F80LAA Datasheet, PDF (119/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Electrical Parameters
4.6.5 External Bus Timing
The following parameters specify the behavior of the XE167xM bus interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Bus Interface Performance Limits
The output frequency at the bus interface pins is limited by the performance of the output
drivers. The fast clock driver (used for CLKOUT) can drive 80-MHz signals, the standard
drivers can drive 40-MHz signals
Therefore, the speed of the EBC must be limited, either by limiting the system frequency
to f_SYS ≤ 80 MHz or by adding waitstates so that signal transitions have a minimum
distance of 12.5 ns.
For a description of the bus protocol and the programming of its variable timing
parameters, please refer to the User’s Manual.
Table 27 EBC Parameters
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
CLKOUT Cycle Time¹⁾
t₅ CC −
1 / f_SYS −
ns
CLKOUT high time
t₆ CC 2
−
−
CLKOUT low time
t₇ CC 2
−
−
CLKOUT rise time
t₈ CC −
−
3
ns
CLKOUT fall time
t₉ CC −
−
3
1) The CLKOUT cycle time is influenced by PLL jitter. For longer periods the relative deviation decreases (see
PLL deviation formula).
CLKOUT
t₅
t₆
t₇
Figure 22 CLKOUT Signal Timing
Data Sheet
119
t₉
t₈
MC_X_ EBCCLKOUT
V2.1, 2011-07