SAK-XE167FM-72F80LAA Datasheet, PDF (137/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Electrical Parameters
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply; C_L= 20 pF.
Table 39 JTAG Interface Timing for Upper Voltage Range
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup to TCK
rising edge
Symbol
Min.
t₁ SR 50¹⁾
t₂ SR 16
t₃ SR 16
t₄ SR −
t₅ SR −
t₆ SR 6
Values
Typ. Max.
−
−
−
−
−
−
−
8
−
8
−
−
Unit Note /
Test Condition
ns
2)
ns
ns
ns
ns
ns
TDI/TMS hold after TCK t₇ SR 6
−
−
ns
rising edge
TDO valid from TCK falling t₈ CC −
edge (propagation delay)³⁾
25
29
ns
TDO high impedance to t₉ CC −
valid output from TCK
falling edge⁴⁾³⁾
25
29
ns
TDO valid output to high t₁₀ CC −
impedance from TCK
falling edge³⁾
25
29
ns
TDO hold after TCK falling t₁₈ CC 5
−
−
ns
edge³⁾
1) The debug interface cannot operate faster than the overall system, therefore t₁ ≥ t_SYS.
2) Under typical conditions, the interface can operate at transfer rates up to 20 MHz.
3) The falling edge on TCK is used to generate the TDO timing.
4) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
137
V2.1, 2011-07