SAK-XE167FM-72F80LAA Datasheet, PDF (112/144 Pages) Infineon Technologies AG – 16-Bit Single-Chip Real Time Signal Controller

XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family / Base Line
Electrical Parameters
Acc. jitter D_T
ns
±9
±8
±7
±6
±5
±4
±3
±2
±1
0
1
fSYS = 33 MHz fSYS = 66 MHz
f_VCO = 66 MHz
fVCO = 132 MHz
Cycles T
20
40
60
80
100
MC_XC 2X_JITTER
Figure 20 Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed C_L = 20 pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
V_DDPB pin 100 and V_SS pin 1) is limited to a peak-to-peak voltage of V_PP = 50 mV.
This can be achieved by appropriate blocking of the supply voltage as close as
possible to the supply pins and using PCB supply and ground planes.
Data Sheet
112
V2.1, 2011-07