XC2361A Datasheet, PDF (47/123 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361A, XC2363A, XC2364A, XC2365A
XC2000 Family Derivatives / Base Line
Functional Description
Table 7
XC236xA Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location¹⁾
Trap
Number
xx’0190_H
64_H / 100_D
xx’0194_H
65_H / 101_D
xx’0198_H
66_H / 102_D
xx’019C_H
67_H / 103_D
SCU External Request 0
SCU_ERU_0IC xx’01A0_H
68_H / 104_D
SCU External Request 1
SCU_ERU_1IC xx’01A4_H
69_H / 105_D
SCU External Request 2
SCU_ERU_2IC xx’01A8_H
6A_H / 106_D
SCU Request 1
SCU_1IC
xx’01AC_H
6B_H / 107_D
SCU Request 0
SCU_0IC
xx’01B0_H
6C_H / 108_D
SCU External Request 3
SCU_ERU_3IC xx’01B4_H
6D_H / 109_D
RTC
RTC_IC
xx’01B8_H
6E_H / 110_D
End of PEC Subchannel
EOPIC
xx’01BC_H
6F_H / 111_D
1) Register VECSEG defines the segment where the vector table is located.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting with a distance of 4 (two words) between two vectors.
Note: Vector locations without an associated interrupt control register are not assigned
and are reserved.
Data Sheet
47
V2.0, 2009-03