XC2361A Datasheet, PDF (36/123 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361A, XC2363A, XC2364A, XC2365A
XC2000 Family Derivatives / Base Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC236xA is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Table 6
XC236xA Memory Map
Address Area
Start Loc. End Loc.
IMB register space
FF’FF00_H
Reserved (Access trap) F0’0000_H
Reserved for EPSRAM E8’8000_H
Emulated PSRAM
E8’0000_H
Reserved for PSRAM E0’8000_H
Program SRAM
E0’0000_H
Reserved for Flash
CD’0000_H
Program Flash 3
CC’0000_H
Program Flash 2
C8’0000_H
Program Flash 1
C4’0000_H
Program Flash 0
C0’0000_H
External memory area 40’0000_H
Available Ext. IO area³⁾ 21’0000_H
FF’FFFF_H
FF’FEFF_H
EF’FFFF_H
E8’7FFF_H
E7’FFFF_H
E0’7FFF_H
DF’FFFF_H
CC’FFFF_H
CB’FFFF_H
C7’FFFF_H
C3’FFFF_H
BF’FFFF_H
3F’FFFF_H
Area Size¹⁾ Notes
256 Bytes –
<1 Mbyte
Minus IMB registers
480 Kbytes Mirrors EPSRAM
32 Kbytes Flash timing
480 Kbytes Mirrors PSRAM
32 Kbytes Maximum speed
<1.25 Mbytes –
64 Kbytes –
256 Kbytes –
256 Kbytes –
256 Kbytes ²⁾
8 Mbytes
–
< 2 Mbytes Minus USIC/CAN
Data Sheet
36
V2.0, 2009-03