XC2361A Datasheet, PDF (106/123 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361A, XC2363A, XC2364A, XC2365A
XC2000 Family Derivatives / Base Line
Electrical Parameters
Table 32 External Bus Cycle Timing for Lower Voltage Range
Parameter
Symbol
Limits
Unit Note
Min. Typ. Max.
Output valid delay for:
RD, WR(L/H)
t₁₀ CC –
20
ns
Output valid delay for:
BHE, ALE
t₁₁ CC –
21
ns
Address output valid delay for:
A23 … A16, A15 … A0
t₁₂ CC –
22
ns
Address output valid delay for:
AD15 … AD0
t₁₃ CC –
22
ns
Output valid delay for:
CS
t₁₄ CC –
13
ns
Data output valid delay for:
AD15 … AD0 (write data, MUX)
t₁₅ CC –
22
ns
Data output valid delay for:
D15 … D0 (write data, DEMUX)
t₁₆ CC –
22
ns
Output hold time for:
RD, WR(L/H)
t₂₀ CC -2
10
ns
Output hold time for:
BHE, ALE
t₂₁ CC -2
10
ns
Address output hold time for:
AD15 … AD0
t₂₃ CC -3
10
ns
Output hold time for:
CS
t₂₄ CC -3
11
ns
Data output hold time for:
D15 … D0, AD15 … AD0
t₂₅ CC -3
10
ns
Input setup time for:
t₃₀ SR 29
READY, D15 … D0, AD15 … AD0
(read data)
–
ns
Input hold time for:
t₃₁ SR 0
READY, D15 … D0, AD15 … AD0
(read data)¹⁾
–
ns
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
106
V2.0, 2009-03