XC2361A Datasheet, PDF (114/123 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2361A, XC2363A, XC2364A, XC2365A
XC2000 Family Derivatives / Base Line
Electrical Parameters
4.6.7 Debug Interface Timing
The debugger can communicate with the XC236xA either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 35 JTAG Interface Timing Parameters for Upper Voltage Range
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
Symbol
Min.
t₁ SR 50
t₂ SR 16
t₃ SR 16
t₄ SR –
t₅ SR –
t₆ SR 6
Values
Typ. Max.
–
–
–
–
–
–
–
8
–
8
–
–
Unit Note /
Test Condition
ns ¹⁾
ns
ns
ns
ns
ns
TDI/TMS hold
t₇ SR 6
–
–
ns
after TCK rising edge
TDO valid
t₈ CC –
after TCK falling edge²⁾
25
29
ns
TDO high imped. to valid t₉ CC –
from TCK falling edge²⁾³⁾
25
29
ns
TDO valid to high imped. t₁₀ CC –
from TCK falling edge²⁾
25
29
ns
TDO hold after
TCK falling edge²⁾
t₁₈ CC 5
–
–
ns
1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
114
V2.0, 2009-03