TC1791 Datasheet, PDF (139/153 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1791
5.3.10
Electrical ParametersAC Parameters
SSC Master/Slave Mode Timing
The SSC parameters are vaild for C_L = 50 pF and strong driver medium edge.
Table 41 SSC Parameters
Parameter
Symbol
Values
SCLK clock period¹⁾²⁾³⁾
t₅₀ CC
MTSR/SLSOx delay form t₅₁ CC
SCLK rising edge
Min.
2x1/
f_FPI
0
Typ.
−
−
Max.
−
8
MRST setup to SCLK
t₅₂ SR 16.5 −
−
latching edge³⁾
MRST hold from SCLK t₅₃ SR 0
−
−
latching edge³⁾
SCLK input clock
period¹⁾³⁾
t₅₄ SR 4 x 1 / −
−
f_FPI
SCLK input clock duty
t₅₅_t₅₄ 45
−
55
cycle
SR
MTSR setup to SCLK
t₅₆ SR 1 / f_FPI −
−
latching edge³⁾⁴⁾
MTSR hold from SCLK t₅₇ SR 1 / f_FPI −
−
latching edge
+5
SLSI setup to first SCLK t₅₈ SR 1 / f_FPI −
−
latching edge
+5
SLSI hold from last SCLK t₅₉ SR 7
−
−
latching edge⁵⁾
MRST delay from SCLK t₆₀ CC 0
−
16.5
shift edge
SLSI to valid data on
t₆₁ CC −
−
16.5
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
Unit Note /
Test Condition
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
Data Sheet
132
V 1.1, 2014-05