TC1791 Datasheet, PDF (127/153 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1791
5.3.4
Phase Locked Loop (PLL)
Electrical ParametersAC Parameters
Table 34 PLL_SysClk Parameters
Parameter
Symbol
Min.
Accumulated Jitter
Modulation frequency
PLL base frequency
D_P CC -7
f_MOD SR 50
f_PLLBASE 50
CC
VCO input frequency
VCO frequency range
f_REF CC 8
f_VCO CC 400
400
Modulation jitter
Total long term jitter
Modulation Amplitude
PLL lock-in time
System frequency
deviation
J_MOD CC −
J_TOT CC −
MA SR 0
t_L CC 14
14
f_SYSD
−
CC
Values
Typ. Max.
−
7
−
200
200 320
Unit Note /
Test Condition
ns
kHz
MHz
−
16
MHz
−
720 MHz with inactive
modulation
−
600 MHz with active
modulation
−
2.5 ns
−
9.5 ns Sum of D_P and
J_MOD
−
2.5
% % of f_VCO
−
200 μs N > 32
−
400 μs N ≤ 32
−
0.01 % with active
modulation
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the SRI-
Bus clock f_SRI) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Data Sheet
120
V 1.1, 2014-05