ICS9P935 Datasheet, PDF (9/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
General I²C serial interface information for the ICS9P935
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4 _(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4 _(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5
(H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X_(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address D4_(H)
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P
stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
Slave Address D4_(H)
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D5_(H)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
Notes:
N Not acknowledge
P
stoP bit
Byte N + X - 1
1.
The IDT clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for verification.
Read-Back will support SMBus block read protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must
be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred.
The Command code and Byte count shown above must be sent, The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935 REV H 12/1/08
9