ICS9P935 Datasheet, PDF (7/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition (see note 1)
T_A = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage
(note 2)
V_DD, A_VDD
V_IL
V_IH
DDRT,DDRC
DDRT,DDRC
V_IN
2.3
2.5
0.4
V_DD/2 + 0.18 2.1
-0.3
Differential input signal
DC - DDRT
0.36
voltage (note 3)
V_ID
AC - DDRT
0.7
Output differential cross-
voltage (note 4)
V_OX
V_DD/2 - 0.15
Input differential cross-
voltage (note 4)
V_IX
V_DD/2 - 0.2 V_DD/2
High level output
current
I_OH
MAX
2.7
V_DD/2 - 0.18
UNITS
V
V
V
V_DD + 0.3
V
V_DD + 0.6
V
V_DD + 0.6
V
V_DD/2 + 0.15 V
V_DD/2 + 0.2
V
-30
mA
Low level output current
I_OL
Operating free-air
temperature
T_A
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VT is the true input level and VCP is the complementary input level.
4. Differential cross-point voltage is expected to track variations of V_DD and is the voltage
at which the differential signal must be crossing.
-30
mA
85
°C
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
7
ICS9P935 REV H 12/1/08