ICS9P935 Datasheet, PDF (1/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

DDR I/DDR II Phase Lock Loop Zero Delay Buffer
DATASHEET
ICS9P935
Description
DDR I/DDR II Zero Delay Clock Buffer
Output Features
• Low skew, low jitter PLL clock driver
• Max frequency supported = 400MHz (DDRII 800)
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Programmable skew through SMBus
• Frequency defect control thorugh SMBus
• Individual output control programmable through SMBus
Key Specifications
• CYCLE - CYCLE jitter: <100ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 48% - 52%
• 28-pin SSOP package
• Available in RoHS compliant packaging
• Operates @ 2.5V or 1.8V
Funtional Block Diagram
Pin Configuration
DDRC0 1
28 GND
DDRT0 2
27 DDRC5
VDD2.5/1.8 3
26 DDRT5
DDRT1 4
25 VDD2.5/1.8
DDRC1 5
24 GND
GND 6
23 DDRC4
VDDA2.5/1.8 7
22 DDRT4
GND 8
21 VDD2.5/1.8
CLK_INT 9
20 SDATA
CLK_INC 10
19 SCLK
VDD2.5/1.8 11
18 FB_IN
DDRT2 12
17 FB_OUT
DDRC2 13
16 DDRT3
GND 14
15 DDRC3
28-SSOP/TSSOP
SCLK
SDATA
Control
Logic
FB_IN
CLK_INT
PLL
CLK_INC
FB_OUT
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
1
ICS9P935 REV H 12/1/08