ICS9P935 Datasheet, PDF (12/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
--
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
--
0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
--
.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
--
.004
VARIATIONS
N
28
D mm.
MIN
MAX
9.60
9.80
D (inch)
MIN
MAX
.378
.386
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9P935yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
12
ICS9P935 REV H 12/1/08