ICS9P935 Datasheet, PDF (13/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Revision History
Rev. Issue Date Description
A
2/8/2007 Final Release.
B
6/4/2007 Fixed various typos.
C 6/14/2007 Added TSSOP Ordering Information.
1. Updated Output Features: Max Frequency Supported.
D 6/20/2007 2. Updated DDRI/DDRII Max Clock Frequency.
1. Updated Supply Voltage.
E
8/16/2007 2. Updated Input High/Low Current Max.
F
9/5/2007 Updated Electrical Specifications.
G 11/19/2007 Updated Serial Interface Information.
H 12/1/2008 Updated Pin Description.
Page #
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12
1
5, 8
3
3-5
9
2
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