ICS9P935 Datasheet, PDF (2/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Pin Description
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin Name
DDRC0
DDRT0
VDD2.5/1.8
DDRT1
DDRC1
GND
VDDA2.5/1.8
GND
CLK_INT
CLK_INC
VDD2.5/1.8
DDRT2
DDRC2
GND
DDRC3
DDRT3
FB_OUT
18
FB_IN
19
SCLK
20
SDATA
21
VDD2.5/1.8
22
DDRT4
23
DDRC4
24
GND
25
VDD2.5/1.8
26
DDRT5
27
DDRC5
28
GND
Type
OUT
OUT
PWR
OUT
OUT
PWR
PWR
PWR
IN
IN
PWR
OUT
OUT
PWR
OUT
OUT
OUT
IN
IN
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
Pin Description
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Output power supply, nominal 2.5V or 1.8V
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Feedback output, dedicated for external feedback.
Single-ended feedback input, provides feedback signal to internal PLL to eliminate
phase error with the input clock.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V or 1.8V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
2
ICS9P935 REV H 12/1/08