ICS9P935 Datasheet, PDF (4/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition (see note1)
T_A = 0 - 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage (note 2)
DC input signal voltage swing
Differential input signal voltage
(note 3)
Output differential cross-voltage
(note 4)
Input differential cross-voltage
(note 4)
V_DDQ, A_VDD
V_IL CLK_INT, CLK_INC, FB_IN
V_IH CLK_INT, CLK_INC, FB_IN
V_IN
V_IN-Diff CLK_INT, CLK_INC
DC - CLK_INT, CLK_INC,
V_ID
FB_IN
AC - CLK_INT, CLK_INC,
FB_IN
V_OX
V_IX
1.7
0.65 x V_DD
-0.3
GND - 0.3
0.3
0.6
V_DD / 2 - 0.1
V_DD/2 - 0.15
High level output current
Low level output current
High Impedance
Output Current
I_OH
I_OL
I_OZ
V_DD=1.9V, V_OUT=V_DD or GND
Operating free-air temperature
T_A
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VTR is the true input level and VCP is the complementary input
level.
4. Differential cross-point voltage is expected to track variations of V_DD and is the voltage
at which the differential signal must be crossing.
TYP
1.8
1.5
MAX
1.9
0.35 x V_DD
V_DD + 0.3
V_DD + 0.3
V_DD + 0.4
UNITS
V
V
V
V
V
V
V_DD + 0.4
V
V_DD / 2 + 0.1 V
V_DD/2 V_DD / 2 + 0.15 V
-9
mA
9
mA
±₁₀
mA
70
°C
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
4
ICS9P935 REV H 12/1/08