ICS9P935 Datasheet, PDF (8/13 Pages) Integrated Device Technology – DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Timing Requirements
T_A = 0 - =70°C; Supply Voltage A_VDD, V_DD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freq_op
2.5V+0.2V @ 25^oC
45
600
Application Frequency
Range
freq_App
2.5V+0.2V @ 25^oC
95
233
Input clock duty cycle
d_tin
40
60
UNITS
MHz
MHz
%
CLK stabilization
T_STAB
15
µs
Switching Characteristics³
PARAMETER
SYMBOL
CONDITION
Low-to high level
propagation delay time
High-to low level propagation
delay time
t_PLH1
t_PLL1
BUF_IN to any output
BUF_IN to any output
Period jitter
Half-period jitter
T_{jit (per)}
t(jit_hper)
100MHz to 200MHz
100MHz to 200MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter¹
Static Phase Offset
Output to Output Skew
t_sl(i)
t_sl(o)
T_cyc-T_cyc 100MHz to 200MHz
t_(static
phase
4
offset)
T_skew
MIN
-30
-100
1
1
-50
-50
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
TYP
3.5
3.5
0
MAX UNITS
ns
ns
30
ps
100 ps
4 V/ns
2 V/ns
50
ps
50
ps
40
ps
IDT^TM/ICS^TM DDR I/DDR II Phase Lock Loop Zero Delay Buffer
8
ICS9P935 REV H 12/1/08