ICS9LPRS501 Datasheet, PDF (9/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
33 VDDSRC_IO
34 SRCT4
35 SRCC4
36 GNDSRC
37 SRCT9
38 SRCC9
39 SRCC11/CR#_G
40 SRCT11/CR#_H
41 SRCT10
42 SRCC10
43 VDDSRC_IO
44 CPU_STOP#/SRCC5
45 PCI_STOP#/SRCT5
46 VDDSRC
47 SRCC6
48 SRCT6
TYPE
DESCRIPTION
PWR Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
I/O True clock of differential SRC clock pair 4
I/O Complement clock of differential SRC clock pair 4
PWR Ground pin for SRC clocks.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled
I/O
in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can
then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled
in byte 3, bit 6 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can
I/O then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration
space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
OUT True clock of differential SRC clock pair.
OUT Cpmplement clock of differential SRC clock pair.
PWR Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin
I/O
6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin
I/O
6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
PWR VDD pin for SRC internal circuits, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
9
1121F—02/23/09