ICS9LPRS501 Datasheet, PDF (5/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
49 VDDCPU_IO
50 CPUC1_F
TYPE
PWR
OUT
DESCRIPTION
Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance
Complement clock of low power differenatial CPU clock pair. This clock will be free-running
during iAMT.
51 CPUT1_F
OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
52 GNDCPU
53 CPUC0
54 CPUT0
55 VDDCPU
56 CK_PWRGD/PD#
57 FSLB/TEST_MODE
58 GNDREF
59 X2
60 X1
61 VDDREF
62 REF0/FSLC/TEST_SEL
63 SDATA
64 SCLK
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Fully Integrated Regulator Connection for Desktop/Mobile Applications
ICS9LPR501
ICS9LPRS501
VDDCPU_IO, Pin 49
NC
PIN 48
1.05V to 3.3V
(+/-5%)
CPU_IO Decoupling
Network
96_IO Decoupling
Network
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 45,36,26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
5
1121F—02/23/09