ICS9LPRS501 Datasheet, PDF (20/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Byte 0 FS Readback and PLL Selection Register
Bit Pin
Name
Description
Type
7-
FSLC
CPU Freq. Sel. Bit (Most Significant)
R
6-
5-
4-
3
2-
1-
0-
FSLB
FSLA
iAMT_EN
Reserved
SRC_Main_SEL
SATA_SEL
PD_Restore
CPU Freq. Sel. Bit
R
CPU Freq. Sel. Bit (Least Significant)
R
Set via SMBus or dynamically by CK505 if
detects dynamic M1
RW
Reserved
RW
Select source for SRC Main
RW
Select source for SATA clock
RW
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold
power-on and go to latches open state
RW
This bit is ignored and treated at '1' if device is in
iAMT mode.
0
See Table 1 : CPU
Frequency Select Table
Legacy Mode
SRC Main = PLL1
SATA = SRC_Main
Configuration Not Saved
1
iAMT Enabled
SRC Main = PLL3
SATA = PLL2
Default
Latch
Latch
Latch
0
0
0
0
Configuration Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin
Name
Description
7 13/14
SRC0_SEL
Select SRC0 or DOT96
6-
PLL1_SSC_SEL
Select 0.5% down or center SSC
5
PLL3_SSC_SEL
Select 0.5% down or center SSC
4
PLL3_CF3
PLL3 Quick Config Bit 3
3
PLL3_CF2
PLL3 Quick Config Bit 2
2
PLL3_CF1
PLL3 Quick Config Bit 1
1
PLL3_CF0
PLL3 Quick Config Bit 0
0
PCI_SEL
PCI_SEL
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
Down spread
1
DOT96
Center spread
Center spread
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
PCI from PLL1
PCI from SRC_MAIN
Default
0
0
0
0
0
0
1
1
Byte 2 Output Enable Register
Bit Pin
Name
Description
7
REF_OE
Output enable for REF, if disabled output is
tri-stated
6
USB_OE
Output enable for USB
5
PCIF5_OE
Output enable for PCI5
4
PCI4_OE
Output enable for PCI4
3
PCI3_OE
Output enable for PCI3
2
PCI2_OE
Output enable for PCI2
1
PCI1_OE
Output enable for PCI1
0
PCI0_OE
Output enable for PCI0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 3 Output Enable Register
Bit Pin
Name
7
SRC11_OE
6
SRC10_OE
5
SRC9_OE
4
SRC8/ITP_OE
3
SRC7_OE
2
SRC6_OE
1
SRC5_OE
0
SRC4_OE
Description
Output enable for SRC11
Output enable for SRC10
Output enable for SRC9
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Output enable for SRC5
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit Pin
Name
Description
7
SRC3_OE
Output enable for SRC3
6
SATA/SRC2_OE
Output enable for SATA/SRC2
5
SRC1_OE
Output enable for SRC1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
3
CPU1_OE
Output enable for CPU1
2
CPU0_OE
Output enable for CPU0
1
PLL1_SSC_ON
Enable PLL1's spread modulation
0
PLL3_SSC_ON
Enable PLL3's spread modulation
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
20
1121F—02/23/09