ICS9LPRS501 Datasheet, PDF (15/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Electrical Characteristics - SE1/2=25MHz
PARAMETER
SYMBOL
CONDITIONS
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Absolute min/max period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
Jitter, Long Term
T_period
T_abs
V_OH
V_OL
I_OH
I_OL
t_SLR
t_FLR
d_t1
t_jcyc-cyc
t_LTJ
25.00MHz output nominal
25.00MHz output nominal
I_OH = -1 mA
I_OL = 1 mA
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V @ 10us delay
MIN
-100
39.99600
39.32360
2.4
-29
29
1
1
45
MAX UNITS NOTES
100
ppm 1,2
40.00400 ns
1
40.67640 ns
1
V
1
0.4
V
1
mA
1
-23
mA
1
mA
1
27
mA
1
4
V/ns
1
4
V/ns
1
55
%
1
500
ps
1
3000
ps
1
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
SMBus Voltage
Low-level Output Voltage
Current sinking at
V_OLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
V_DD
V_OLSMB
I_PULLUP
T_RI2C
T_FI2C
F_SMBUS
@ I_PULLUP
SMB Data Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
Block Mode
MIN
MAX UNITS Notes
2.7
5.5
V
1
0.4
V
1
4
mA
1
1000
ns
1
300
ns
1
100
kHz
1
Notes on Electrical Characteristics:
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Slew rate measured through Vswing centered around differential zero}
3 _{Vxabs is defined as the voltage where CLK = CLK#}
4 _{Only applies to the differential rising edge (CLK rising and CLK# falling)}
5 _{Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of}
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
6 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
7 _{Operation under these conditions is neither implied, nor guaranteed.}
8 _{Maximum input voltage is not to exceed maximum VDD}
9 _{See PCI Clock-to-Clock Delay Figure}
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
15
1121F—02/23/09