ICS9LPRS501 Datasheet, PDF (8/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
17 USB_48MHz/FSLA
18 GND48
19 VDD96_IO
20 DOTT_96/SRCT0
21 DOTC_96/SRCC0
22 GND
23 VDD
24 SRCT1/SE1
25 SRCC1/SE2
26 GND
27 VDDPLL3_IO
28 SRCT2/SATAT
29 SRCC2/SATAC
30 GNDSRC
31 SRCT3/CR#_C
32 SRCC3/CR#_D
TYPE
DESCRIPTION
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
PWR Ground pin for the 48MHz outputs.
PWR Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function
OUT
may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin
OUT
function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
PWR Ground pin for the DOT96 clocks.
PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
OUT
True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz
SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
OUT
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100
MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
PWR Ground pin for SRC / SE1 and SE2 clocks, PLL3.
PWR Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance
OUT True clock of differential SRC/SATA clock pair.
OUT Complement clock of differential SRC/SATA clock pair.
PWR Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3
output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using
I/O
the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4
pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3
output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using
I/O the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
8
1121F—02/23/09