ICS9LPRS501 Datasheet, PDF (10/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
49 GNDSRC
50 SRCC7/CR#_E
TYPE
PWR Ground for SRC clocks
DESCRIPTION
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled
I/O
in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can
then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
51 SRCT7/CR#_F
52 VDDSRC_IO
53 CPUC2_ITP/SRCC8
54 CPUT2_ITP/SRCT8
55 NC
56 VDDCPU_IO
57 CPUC1_F
58 CPUT1_F
59 GNDCPU
60 CPUC0
61 CPUT0
62 VDDCPU
63 CK_PWRGD/PD#
64 FSLB/TEST_MODE
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled
I/O
in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then
be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
PWR
OUT
Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The
function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
N/A No Connect
PWR Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during
iAMT.
OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
PWR Ground Pin for CPU Outputs
OUT Complement clock of low power differential CPU clock pair.
OUT True clock of low power differential CPU clock pair.
PWR Power Supply 3.3V nominal.
IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
IN Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while
in test mode. Refer to Test Clarification Table.
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
10
1121F—02/23/09