ICS9LPRS501 Datasheet, PDF (22/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Byte 10 CK505 Rev 0.85 Functions (ICS Rev H Silicon and Higher)
Bit Pin
Name
Description
7
SRC5_EN Readback
Readback of SRC5 enable latch
6
Reserved
5
Reserved
4
Reserved
Reserved
3
Reserved
2
Reserved
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
Type
R
RW
RW
RW
RW
RW
RW
RW
0
CPU/PCI Stop Enabled
TBD
TBD
TBD
TBD
TBD
Free Running
Free Running
Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher)
Bit Pin
Name
Description
7
Reserved
6
Reserved
5
Reserved
Reserved
4
Reserved
3
CPU2_iAMT_EN
Enables CPU2(ITP) output in iAMT state (M1)
2
CPU1_iAMT_EN
Enables CPU1 output in iAMT state (M1)
1
PCIe-Gen2
PCIe-Gen2 status
0
CPU2 Stop Enable Enables control of CPU2(ITP) with CPU_STOP#
Type
RW
RW
RW
RW
RW
RW
R
RW
0
TBD
TBD
TBD
TBD
Off in iAMT
Off in iAMT
non-Gen2
Free Running
Byte 12 Byte Count Register
Bit Pin
Name
Description
Type
0
7
Reserved
RW
6
Reserved
RW
5
BC5
RW
4
BC4
RW
3
BC3
Read Back byte count register
RW
2
BC2
RW
1
BC1
RW
0
BC0
RW
Byte 13 CK505 PLL1 M/N Programming Register
Bit Pin
Name
Description
Type
0
7
N Div8
N Divider 8
RW
-
6
N Div9
N Divider 9
RW
-
5
M Div5
RW
-
4
M Div4
The decimal representation of M Div (5:0) is equal ^RW
-
3
2
1
M Div3
M Div2
M Div1
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
RW
RW
RW
-
-
-
0
M Div0
RW
-
Byte 14 CK505 PLL1 M/N Programming Register
Bit Pin
Name
Description
Type
0
7
N Div7
RW
-
6
N Div6
RW
-
5
N Div5
The decimal representation of N Div (9:0) is equal ^RW
-
4
N Div4
to VCO divider value. Default at power up = latch- ^RW
-
3
N Div3
in or Byte 0 Rom table.
RW
-
2
N Div2
RW
-
1
N Div1
RW
-
0
N Div0
RW
-
Byte 15 CK505 PLL1 Spread Spectrum Control Register
Bit Pin
Name
Description
Type
0
7
SSP7
RW
-
6
SSP6
RW
-
5
SSP5
These Spread Spectrum bits will program the ^RW
-
4
SSP4
spread pecentage. Contact ICS for the correct ^RW
-
3
SSP3
values.
RW
-
2
SSP2
RW
-
1
SSP1
RW
-
0
SSP0
RW
-
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
22
1
SRC5 Enabled
TBD
TBD
TBD
TBD
TBD
Stoppable
Stoppable
Default
Latch
0
0
0
0
0
1
1
1
TBD
TBD
TBD
TBD
Free running in iAMT
Free running in iAMT
PCIe Gen2 compliant
Stoppable
Default
0
0
0
0
0
1
0
1
1
Default
0
0
0
0
1
1
0
1
1
Default
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
1
Default
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
1
Default
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
1121F—02/23/09