ICS9LPRS501 Datasheet, PDF (21/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Byte 5 Clock Request Enable/Configuration Register
Bit Pin
Name
Description
7
CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 1 for this bit to take effect
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
5
CR#_B_EN
Enable CR#_B (clk req)
4
CR#_B_SEL
Sets CR#_B -> SRC1 or SRC4
3
CR#_C_EN
Enable CR#_C (clk req)
2
CR#_C_SEL
Sets CR#_C -> SRC0 or SRC2
1
CR#_D_EN
Enable CR#_D (clk req)
0
CR#_D_SEL
Sets CR#_D -> SRC1 or SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit Pin
Name
Description
Type
7
CR#_E_EN
Enable CR#_E (clk req) -> SRC6
RW
6
CR#_F_EN
Enable CR#_F (clk req) -> SRC8
RW
5
CR#_G_EN
Enable CR#_G (clk req) -> SRC9
RW
4
CR#_H_EN
Enable CR#_H (clk req) -> SRC10
RW
3
Reserved
Reserved
RW
2
Reserved
Reserved
RW
1
SSCD_STP_CRTL
If set, SSCD (SRC1) stops with PCI_STOP# RW
(SRC1)
If set, SRCs (except SRC1) stop with
0
SRC_STP_CRTL
PCI_STOP#
RW
Byte 7 Vendor ID/ Revision ID
Bit Pin
Name
7
Rev Code Bit 3
6
Rev Code Bit 2
5
Rev Code Bit 1
4
Rev Code Bit 0
3
Vendor ID bit 3
2
Vendor ID bit 2
1
Vendor ID bit 1
0
Vendor ID bit 0
Description
Revision ID
Vendor ID
ICS is 0001, binary
Type
R
R
R
R
R
R
R
R
Byte 8 Device ID and Output Enable Register
Bit Pin
Name
Description
7
6
5
4
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Table of Device identifier codes, used for
differentiating between CK505 package
options, etc.
3
Reserved
Reserved
2
Reserved
Reserved
1
SE1_OE
0
SE2_OE
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
Byte 9 Output Control Register
Bit Pin
Name
Description
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
6
TME_Readback
Truested Mode Enable (TME) strap status
5
Reserved
Reserved
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
3
Test Mode Entry
Allows entry into test mode, ignores
FSB/TestMode
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
1
IO_VOUT1
IO Output Voltage Select
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
Type
RW
R
RW
RW
RW
RW
RW
RW
0
Disable CR#_A
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
Default
0
0
0
0
0
0
0
0
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
Free Running
Free Running
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
0
0
0
0
0
0
0
0
0
1
Vendor specific
Default
X
X
X
X
0
0
0
1
0
1
See Device ID Table
-
-
Disabled
Disabled
-
-
Enabled
Enabled
Default
0
0
0
1
0
0
0
0
0
Free running
normal operation
-
Outputs HI-Z
1
Stops with PCI_STOP#
assertion
no overclocking
-
Outputs = REF/N
Default
0
0
1
0
Normal operation
Test mode
0
See Table 3: V_IO Selection
1
(Default is 0.8V)
0
1
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
21
1121F—02/23/09