ICS9LPRS501 Datasheet, PDF (16/28 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Table 1: CPU Frequency Select Table
FSLC²
B0b7
FSLB¹
B0b6
FSLA¹
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66 100.00 33.33 14.318 48.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_LC is a three-level input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
Table 2: PLL3 Quick Configuration
B1b4
B1b3
B1b2
B1b1
Pin 17
MHz
0
0
0
0
0
0
0
1
100.00
0
0
1
0
100.00
0
0
1
1
100.00
0
1
0
0
100.00
0
1
0
1
100.00
0
1
1
0
100.00
0
1
1
1
N/A
1
0
0
0
24.576
1
0
0
1
24.576
1
0
1
0
98.304
1
0
1
1
27.000
1
1
0
0
25.000
1
1
0
1
N/A
1
1
1
0
N/A
1
1
1
1
N/A
Pin 18
MHz
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
98.304
98.304
27.000
25.000
N/A
N/A
N/A
Spread
%
Comment
PLL 3 disabled
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0.5% Down Spread
Only SRCCLK1 from PLL3
1% Down Spread
Only SRCCLK1 from PLL3
1.5% Down Spread
Only SRCCLK1 from PLL3
2% Down Spread
Only SRCCLK1 from PLL3
2.5% Down Spread
Only SRCCLK1 from PLL3
N/A
N/A
None
24.576Mhz on SE1 and SE2
None
24.576Mhz on SE1, 98.304Mhz on SE2
None
98.304Mhz on SE1 and SE2
None
27Mhz on SE1 and SE2
None
25Mhz on SE1 and SE2
N/A
N/A
N/A
N/A
N/A
N/A
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
16
1121F—02/23/09