ICS844S42I Datasheet, PDF (9/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Programming the I²C Interface
Table 3I. I²C Slave Address Table
Bit 7 6 5 4 3
2
1
0
Value 1 0 1 1 0 ADR1 ADR0 R/W
The ICS844S42I acts as a slave device at the I²C bus. The register
file is reset to its default values at power-up by an integrated
power-on reset circuit or by applying an external device reset signal
(nMR).The 7-bit I²C slave address of the ICS844S42I synthesizer is
a combination of a 5-bit fixed addresses and two variable bits which
are set by the hardware pins ADR[1:0]. Bit 0 of the ICS844S42I
slave address is used by the bus controller to select either the read
or write mode. ‘0’ indicates a transmission (I²C-WRITE) to the
ICS844S42I. “1” indicates a request for data (I²C-READ) from the
synthesizer. The hardware pins ADR1 and ADR0 and should be
individually set by the user to avoid address conflicts of multiple
ICS844S42I devices on the same I²C bus.
Each access to the I²C register file must read or write the entire four
register bytes at one time. Each transfer starts with register 0x00H,
followed by register 0x01H, until register 0x02H. Addressing
individual bytes is not supported. The bytes will program internal part
circuitry upon receipt of all three bytes and a given I²C bus <STOP>
signal.
Device Startup
General Device Configuration: It is recommended to reset the
ICS844S42I after the system powers up. The device acquires an
initial PLL divider configuration through the parallel interface pins
M[9:0], NA[2:0], NB[2:0] and P^NOTE1 with the low-to-high transition of
nMR^NOTE2. PLL frequency lock is achieved within the specified lock
time (t_LOCK) and is indicated by an assertion of the LOCK_DT signal
which completes the startup procedure. The output frequency can
be reconfigured at any time through either the parallel or the serial
interface.
Starting-Up Using the Parallel Interface
The simplest way to use the ICS844S42I is through the parallel
interface. The serial interface pins (SDA, SDL, and ADR[1:0]) can be
left open and nPLOAD is set to logic low. After the release of nMR
and at any other time the PLL and output frequency configuration is
directly set to through the M[9:0], NA[2:0], NB[2:0] and P pins.
Table 3J. REF_SEL Configuration Table
REF_SEL Operation
0
Selects REF_CLK input as reference frequency
input
1 (default) Selects the XTAL interface as reference frequency
Table 3K. nBYPASS Configuration Table
nBYPASS Operation
0 (default) ^{fQA, fQB = ((fREF ÷ P) * M) ÷ NA, NB}
PLL operation
1
f_QA, f_QB = f_REF ÷ NA, NB
PLL is bypassed, AC specifications do not apply
The nBYPASS control should be set to logic LOW for normal
operation. nBYPASS = 1 enables the PLL bypass mode for factory
test. In PLL bypass mode, the output frequency is equal to the input
frequency divided by NA, NB and frequency multiplication is
disabled.
Table 3L. nMR Configuration Table
nMR Operation
0
The device is reset and the default settings are
loaded into the I²C file (low to high transition of nMR)
1 (default) Normal operation
The output type and output voltage levels of both outputs are
configured through the configuration input LEV_SEL. LEV_SEL
connected to logic high results in LVPECL output levels and
LEV_SEL connected to logic low results in LVDS output levels of
both QA and QB differential outputs.
Table 3M. LEV_SEL Configuration Table
LEV_SEL Operation
0 (default) QA, QB outputs are LVDS compatible
1
QA, QB outputs are LVPECL compatible
Table 3N. LOCK_DT Configuration Table
LOCK_DT Operation
0
Device is not locked to the input reference clock
1
Device is locked to the input reference clock
NOTE 1: The parallel interface pins M[9:0], NA[2:0], NB[2:0] and P may be left open (floating). In this case the initial PLL configuration will have the default
setting of M = 625MHz, P = 1 (÷4), NA[2:0] = 000 (÷1), NB[2:0] = 000 (÷1), resulting in an internal VCO frequency of 2500MHz (f_REF = 16MHz) and an output
frequency of 2500MHz at both outputs.
NOTE 2: The initial PLL configuration is independent on the selected programming mode (nPLOAD low or high).
ICS844S42BKI REVISION A FEBRUARY 21, 2012
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©2012 Integrated Device Technology, Inc.