ICS844S42I Datasheet, PDF (3/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 7, 16, 27, 34,
35, 36, 37
GND
Power
Power supply ground.
2, 4, 29, 42, 43
nc
Unused
Do not connect.
3
nBYPASS
Input Pulldown PLL bypass. LVCMOS/LVTTL interface levels.
5, 14, 15, 28
6
V_DD
REF_CLK
Power
Input
Digital power supply pins.
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
8
REF_SEL
Input
Pullup Reference select pin. LVCMOS/LVTTL interface levels.
9,
XTAL_IN
10
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
11
nMR
Input
Pullup
Master reset. nMR resets the I²C, output dividers and the LOCK_DT.
LVCMOS/LVTTL interface levels.
12
LOCK_DT
Output
Lock detect output. LVCMOS/LVTTL interface levels.
13
LEV_SEL
Input
Pulldown
Output level select (LVDS and LVPECL).
LVCMOS/LVTTL interface levels.
17
P
Input
Pullup Parallel configuration of PLL pre-divider. LVCMOS/LVTTL interface levels.
18, 19, 20
NA0, NA1, NA2 Input
Pulldown
Parallel configuration of QA output dividers.
LVCMOS/LVTTL interface levels.
21, 22, 23
NB0, NB1, NB2 Input
Pulldown
Parallel configuration of QB output dividers.
LVCMOS/LVTTL interface levels.
24
SDA
I/O
Pullup I²C data input/output pin.LVCMOS/LVTTL interface levels.
25
SCL
I/O
Pullup I²C clock.LVCMOS/LVTTL interface levels.
26
nPLOAD
Input Pulldown Selects the programming interface. LVCMOS/LVTTL interface levels.
30, 31
32, 33
V_DDOB
nQB, QB
Power
Output
Bank B output power supply pins.
QB differential clock output pair. LVPECL or LVDS interface levels.
38, 39
nQA, QA
Output
QA differential clock output pair. LVPECL or LVDS interface levels.
40, 41
44, 48, 49,
50, 53
45, 46, 47,
51, 52
54, 55
V_DDOA
M0, M4, M5,
M6, M9
M1, M2, M3,
M7, M8
ADR0, ADR1
Power
Input
Input
Input
Bank A output power supply pins.
Pullup
Pulldown
Pulldown
Parallel configuration of PLL feedback dividers.
LVCMOS/LVTTL interface levels.
Bits 2 and 1 of the device I²C address. LVCMOS/LVTTL interface levels.
56
V_DDA
Power
Internal PLL power supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS844S42BKI REVISION A FEBRUARY 21, 2012
3
©2012 Integrated Device Technology, Inc.