ICS844S42I Datasheet, PDF (6/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Example Output Frequency Configuration
If a single reference frequency of 16MHz is available, an output
frequency at QA of 2500MHz and a small frequency granularity is
desired, the following steps would be taken to identify the
appropriate P, M, and N configuration:
1. Use Table 3A to select the output divider, NA, that matches the
desired output frequency or frequency range. According to Table 3A
a target output frequency of 2500MHz falls in the f_OUT range of
1296MHz to 2592MHz and requires to set NA = 1.
2. Calculate the VCO frequency f_VCO = f_OUT · NA, which is 2500MHz
in this example.
3. Determine the PLL feedback divider: M = f_VCO ÷ P. The smallest
possible output granularity in this example calculation is 4MHz (set P
= 4). M calculates to a value of 2500MHz ÷ 4 = 625MHz.
4. Configure the ICS844S42I with the obtained settings:
• M[9:0] = 1001110001b (binary number for M = 625)
• NA[2:0] = 000 (÷1 divider, see Table 3C)
• P = 1 (÷4 divider, see Table 3B)
• NB[2:0] = 111 will stop (disable) the QB output
5. Use either parallel or serial interface to apply the setting.
The I²C configuration byte for this examples are:
0x00 = 01110001b, 0x01 = 10111000b and 0x02 = 10000000b. See
Table 3H for a register map.
PLL Divider Configuration
Table 3B. Pre-Divider (P) Table
P
Pre-Divider P Operation
0
1 (default)
2
f_PD = f_REF ÷ 2
4
f_PD = f_REF ÷ 4
Table 3C. Post-Divider (Nx) Table
NA, NB
2
1
0
0 (default) 0 (default) 0 (default)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Post-Divider
NA, NB Operation
1
f_QA, f_QB = f_VCO ÷ 1
2
f_QA, f_QB = f_VCO ÷ 2
3
f_QA, f_QB = f_VCO ÷ 3
6
f_QA, f_QB = f_VCO ÷ 6
4
f_QA, f_QB = f_VCO ÷ 4
8
f_QA, f_QB = f_VCO ÷ 8
16
f_QA, f_QB = f_VCO ÷ 16
N/A
Output stopped in logic low state
ICS844S42BKI REVISION A FEBRUARY 21, 2012
6
©2012 Integrated Device Technology, Inc.