ICS844S42I Datasheet, PDF (7/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Programming the ICS844S42I
The ICS844S42I has a parallel and a serial configuration interface.
The purpose of the parallel interface is to directly configure the PLL
dividers through hardware pins without the overhead of a serial
protocol. At device startup, the device always obtains an initial PLL
frequency configuration through the parallel interface. The parallel
interface does not support reading the PLL configuration. The serial
interface is I²C compatible. It allows reading and writing devices
settings by accessing internal device registers. The serial interface is
designed for host-controller access to the synthesizer frequency
settings, for instance, in frequency-margining applications.
Using the Parallel Interface
The parallel interface supports write-access to the PLL frequency
setting directly through 17 configuration pins (P, M[9:0], NA[2:0], and
NB[2:0]). The parallel interface must be enabled by setting nPLOAD
to logic low level. During nPLOAD = 0, any change of the logical
state of the P, M[9:0], NA[2:0] and NB[2:0] pins will immediately
affect the internal PLL divider settings, resulting in a change of the
internal VCO frequency and the output frequency. The parallel
interface mode disables the I²C write-access to the internal
registers; however, I²C read-access to the internal configuration
registers is enabled. Upon startup, when the device reset signal is
released (rising edge of the nMR signal), the device reads its startup
configuration through the parallel interface and independent of the
state of nPLOAD. It is recommended to provide a valid PLL
configuration for startup. If the parallel interface pins are left open, a
default PLL configuration will be loaded. After the low-to-high
transition of nPLOAD, the configuration pins have no more effect and
the configuration registers are made accessible through the serial
interface.
Table 3D. PLL Feedback Divider (M) Configuration Table
M Bits
9
8
7
6
5
4
3
2
1
0
Pin
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Default
1
0
0
1
1
1
0
0
0
1
Table 3E. PLL Post-Divider (NA) Configuration Table
NA Bits
2
1
0
Pin
NA2
NA1
NA0
Default
0
0
0
Table 3F. PLL Post-Divider (NB) Configuration Table
NB Bits
2
1
0
Pin
NB2
NB1
NB0
Default
0
0
0
Table 3G. PLL Pre-Divider (P) Configuration Table
P
Pin
P
Default
1
ICS844S42BKI REVISION A FEBRUARY 21, 2012
7
©2012 Integrated Device Technology, Inc.