ICS844S42I Datasheet, PDF (8/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Using the I²C Interface
nPLOAD = 1 enables the programming and monitoring of the
internal registers through the I²C interface. Device register access
(write and read) is possible through the 2-wire interface using SDA
(configuration data) and SCL (configuration clock) signals. The
ICS844S42I acts as a slave device at the I²C bus. For further
information on I²C it is recommended to refer to the I²C bus
specification (version 2.1).
nPLOAD = 0 disables the I²C-write-access to the configuration
registers and any data written into the register is ignored. However,
the ICS844S42I is still visible at the I²C interface and I²C transfers
are acknowledged by the device. Read-access to the internal
registers during nPLOAD = 0 (parallel programming mode) is
supported. Note that the device automatically obtains a configuration
using the parallel interface upon the release of the device reset
(rising edge of nMR) and independent on the state of nPLOAD.
Changing the state of the nPLOAD input is not supported when the
device performs any transactions on the I²C interface.
Programming Model and Register Set
The synthesizer contains three fully accessible configuration
registers (0x00 through 0x02). Programming the synthesizer
frequency through the I²C interface is a one step process at which all
registers are written at once by a single I²C transaction. The PLL
frequency is affected as a result of the completion of the entire three
register file write access at the end of writing byte 0x02. The
configuration registers are read as a single I²C transaction. All
registers are read back-to-back. Note that the synthesizer does not
check any boundary conditions such as the VCO frequency range.
Writing the PLL registers could result in invalid VCO frequencies
(VCO frequency beyond lock range).
Register Map
It is always required to configure the entire ICS844S42I register file
(0x00, 0x01, 0x02), addressing single register bytes is not
supported. Writing any information to the bits 2, 1 and 0 in register
0x02 is ignored. These bits indicate information updated by the
synthesizer (bit 2 is the PLL lock status, bits 1 and 0 are copies of the
ADR[1:0] pin status).
Table 3H. Register File Table
Register Address
7
0x00H
M7
Default
0
0x01H
M9
Default
1
0x02H
P
Default
1
6
M6
1
M8
0
RES
0
5
M5
1
NA2
0
RES
0
4
M4
1
NA1
0
RES
0
3
M3
0
NA0
0
RES
0
2
M2
0
NB2
0
LOCK
0
1
M1
0
NB1
0
ADR1
0
0
M0
1
NB0
0
ADR0
0
Access
R/W
R/W
R/W
I²C Register Access in Parallel Mode
The ICS844S42I supports the configuration of the synthesizer
through the parallel interface (nPLOAD = 0) and serial interface
(nPLOAD = 1). Register contents and the divider configurations are
not changed when the user switches from parallel mode to serial
mode. However, when switching from serial mode to parallel mode,
the PLL dividers immediately reflect the logical state of the hardware
pins M[9:0], NA[2:0], NB[2:0], and P. Applications using the parallel
interface to obtain a PLL configuration can use the serial interface to
verify the divider settings. In parallel mode (nPLOAD = 0), the
ICS844S42I allows read-access to the registers through I²C (if
nPLOAD = 0), the current PLL configuration is stored in the
registers. After changing from parallel to serial mode (nPLOAD = 1),
the last PLL configuration is still stored in the registers. The user now
has full write and read access to both configuration registers through
the I²C bus and can change the configuration at any time.
ICS844S42BKI REVISION A FEBRUARY 21, 2012
8
©2012 Integrated Device Technology, Inc.