ICS844S42I Datasheet, PDF (4/27 Pages) Integrated Device Technology – On-chip crystal oscillator for reference frequency generation

ICS844S42I Data Sheet
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance LOCK_DT
Test Conditions
DUAL OUTPUT RF FREQUENCY SYNTHESIZER
Minimum
Typical
2
51
51
20
Maximum
Units
pF
k
k

Functional Description
The ICS844S42I is a programmable high-frequency clock source
(clock synthesizer). The internal PLL generates a high frequency
output signal based on a low-frequency reference signal. The
frequency of the output signal is programmable and can be changed
on the fly for frequency margining purpose. The internal crystal
oscillator uses the parallel-resonance external quartz crystal as the
basis of its frequency reference. Alternatively, an LVCMOS
compatible clock signal can be used as a PLL reference signal. The
frequency of the internal crystal oscillator is divided by a selectable
divider and then multiplied by the PLL. The internal oscillator within
the PLL operates over a range of 1296 MHz to 2592 MHz. Its output
is scaled by two independent dividers that are configured by either
the I2C or parallel interfaces. The crystal oscillator frequency f_XTAL,
the PLL pre-divider P, the feedback-divider M, and the PLL
post-dividers NA, NB determine the output frequency. The feedback
path of the PLL is internal.
The PLL post-dividers NA and NB are configured through either the
I²C or the parallel interfaces, and each can provide one of seven
division ratios (1, 2, 3, 4, 6, 8, 16) and can stop the output clock in a
logic low state. The divider extends the performance of the part while
providing a typical 50% duty cycle. The high-frequency outputs, QA
and QB, are differential and are capable of driving a pair of
transmission lines. The differential outputs are configured as LVDS
or LVPECL by the control input LEV_SEL. The positive supply
voltage for the internal PLL is separated from the power supply for
the core logic and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I²C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB[2:0] and
P parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I²C interface. The
serial interface is I²C compatible and provides read and write access
to the internal PLL configuration registers.The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK_DT output.
ICS844S42BKI REVISION A FEBRUARY 21, 2012
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©2012 Integrated Device Technology, Inc.