ICS874S02I Datasheet, PDF (8/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
V_DD
DC Input LVDS
out
➤
100
V_OD/∆ V_OD
out
V_DD
DC Input LVDS
Differential Output Voltage Setup
Offset Voltage Setup
out
➤
out
V_OS/∆ V_OS
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
IDT™ / ICS™ LVDS CLOCK GENERATOR
8
ICS874S02BMI REV. AOCTOBER 16, 2008