ICS874S02I Datasheet, PDF (10/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, and
other differential signals. Both signals must meet the V_PP and
V_CMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
3.3V
R1
R2
50
50
CLK
nCLK
HiPerClockS
Input
3A. HiPerClockS CLK/nCLK Input Driven by an IDT
Open Emitter HiPerClockS LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50
50
nCLK
HiPerClockS
Input
R2
50
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
HiPerClockS
R1
R2
84
84
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Receiver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
CLK
R1
R2
120
120
nCLK
HiPerClockS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ICS874S02BMI REV. AOCTOBER 16, 2008