ICS874S02I Datasheet, PDF (11/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
Schematic Example
The schematic of the ICS874S02I layout example is shown in
Figure 5A. The ICS874S02I recommended PCB board layout for
this example is shown in Figure 5B. This layout example is used as
a general guideline. The layout in the actual system will depend on
the selected component types and the density of the P.C. board.
3.3V
(155.52 MHz)
Zo = 50 Ohm
Zo = 50 Ohm
3.3V PECL Driv er
SP = Space (i.e. not intstalled)
VDD
R8
R9
50
50
R10
50
U1
1
2 ^CLK
SEL2
3
4
5
6
nCLK
MR
nFB_IN
FB_IN
VDDO
7
8
9
10
SEL2
VDDO
nQFB
QFB
GND
R2
IICCSS87445SB0-21I
100
20
SEL1 ₁₉
SEL0
VDDI
PLL_SEL
VDDA
18
17
16
15
SEL3
GND
Q
nQ
14
13
12
11
VDDO
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
C1
0.1uF
C11
0.01u
R7 VDD
10
C16
10u
(77.76 MHz)
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
Bypass capacitors located
near the power pins
(U1-7)
(U1-11)
VDDO
C4
0.1uF
C2
0.1uF
VDD=3.3V
VDDO=3.3V
SEL[3:0] = 0101,
Divide by 2
+
R4
100
-
LVDS_input
Zo = 100 Ohm Dif f erential
Figure 5A. ICS874S02I LVDS Zero Delay Buffer Schematic Example
IDT™ / ICS™ LVDS CLOCK GENERATOR
11
ICS874S02BMI REV. AOCTOBER 16, 2008