ICS874S02I Datasheet, PDF (3/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
500 - 1000
250 - 500
125 - 250
62.5 - 125
500 - 1000
250 - 500
125 - 250
500 - 1000
250 - 500
500 - 1000
250 - 500
125 - 250
62.5 - 125
125 - 250
62.5 - 125
62.5 - 125
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
Outputs
PLL_SEL = 1
PLL Enable Mode
Q/nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
IDT™ / ICS™ LVDS CLOCK GENERATOR
3
ICS874S02BMI REV. AOCTOBER 16, 2008