ICS874S02I Datasheet, PDF (7/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
3.3V±5%
POWER SUPPLY
+ Float GND –
V_DD,
V_DDO
V_DDA
LVDS
SCOPE
Qx
nQx
V_DD
nCLK
V
PP
CLK
GND
Cross Points
V
CMR
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
nCLK
V_OH
CLK
V_OL
nFB_IN
V_OH
FB_IN
V_OL
➤ t (Ø)
tjit(Ø) =  t(Ø) – t(Ø) mean= Phase Jitter
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Static Phase Offset
nQ, nQFB
Q, QFB
tcycle n
➤
tcycle n+1
➤
| | ^{tjit(cc) =} tcycle n – tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
nQ, nQFB
20%
Q, QFB
80%
t_R
Output Rise/Fall Time
80%
t_F
V_OD
20%
nQ, nQFB
Q, QFB
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Output Duty Cycle/Pulse Width/Period
IDT™ / ICS™ LVDS CLOCK GENERATOR
7
ICS874S02BMI REV. AOCTOBER 16, 2008