ICS874S02I Datasheet, PDF (2/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK
Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
3
MR
Input
Pulldown
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
4
nFB_IN
Input
Pullup
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 8.
5
FB_IN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9.
6, 15,
19, 20
SEL2, SEL3,
SEL0, SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11
8, 9
V_DDO
nQFB, QFB
Power
Output
Output supply pins.
Differential feedback output pair. HSTL interface levels.
10, 14
GND
Power
Power supply ground.
12, 13
nQ, Q
Output
Differential clock output pair. HSTL interface levels.
16
V_DDA
Power
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
17
PLL_SEL
Input
Pullup dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
18
V_DD
Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
kΩ
kΩ
IDT™ / ICS™ LVDS CLOCK GENERATOR
2
ICS874S02BMI REV. AOCTOBER 16, 2008