ICS874S02I Datasheet, PDF (4/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
SEL3
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q/nQ
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
IDT™ / ICS™ LVDS CLOCK GENERATOR
4
ICS874S02BMI REV. AOCTOBER 16, 2008