ICS874S02I Datasheet, PDF (6/16 Pages) Integrated Device Technology – One differential clock input pair

ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 4C. Differential DC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
I_IH
I_IL
V_PP
V_CMR
Input High Current
CLK, FB_IN
nCLK, nFB_IN
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-10
-150
0.15
GND + 0.5
NOTE 1: V_IL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V_IH.
Maximum
150
10
1.3
V_DD – 0.85
Units
µA
µA
µA
µA
V
V
Table 4D. LVDS DC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
∆V_OD
V_OS
∆V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
350
1.20
Typical
450
1.33
Maximum
550
50
1.45
50
Units
mV
mV
V
mV
Table 5. Input Frequency Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
PLL_SEL = 1
62.5
F_IN
Input Frequency CLK/nCLK
PLL_SEL = 0
Maximum
1000
1000
Units
MHz
MHz
Table 6. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
f_OUT
tsk(Ø)
Output Frequency
Static Phase Offset; NOTE 1, 2
PLL_SEL = 1
62.5
-100
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
t_L
t_R / t_F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
47
Typical
Maximum
1000
100
35
1
250
53
Units
MHz
ps
ps
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked
and the input reference frequency is stable.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVDS CLOCK GENERATOR
6
ICS874S02BMI REV. AOCTOBER 16, 2008