ICS814S208I Datasheet, PDF (8/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6. AC Characteristics, V_DD = 3.3V±5%, V_DDOL = 1.8V±0.2V, 2.5V±5% or 3.3V±5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_VCO
f_OUT
VCO Frequency
Output Frequency
QB[0:7],
nQB[0:7]
QA, nQA
BYPASS = 0
N_SEL = 0
N_SEL = 1
BYPASS = 0
570
614.4
640
114
122.88
128
142.5
153.6
160
28.5
30.72
32
f_REF
Reference Frequency
BYPASS = 0
122.88MHz, Integration Range:
1kHz – 40MHz
28.5
30.72
32
0.695
0.96
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
122.88MHz, Integration Range:
12kHz – 20MHz
153.6MHz, Integration Range:
1kHz – 40MHz
0.650
0.89
0.714
0.93
153.6MHz, Integration Range:
12kHz – 20MHz
0.642
0.89
122.88MHz, Offset: 100Hz
-91
Φ_N
Single-Side Band Noise Power
122.88MHz, Offset: 1kHz
122.88MHz, Offset: 10kHz
-118
-130
122.88MHz, Offset: 100kHz
-128
QA, nQA
2.1
4.0
tjit(per) Period Jitter, RMS QBx, nQBx
2.3
4.8
QBx, nQBx
at 122.88MHz
2.3
4.0
TIE
Time Interval Error
Accumulated Period Jitter,
10⁶ Samples
±9
±30
t_PD
Propagation Delay; NOTE 2
REF_CLK, nREF_CLK to QA, nQA,
BYPASS = 1, REF_SEL = 1
550
770
950
tsk(o) Output Skew; NOTE 3, 4
BYPASS = 0
25
100
tsk(b) Bank Skew; NOTE 4, 5
25
100
t_R / t_F
t_LOCK
odc
Output Rise/Fall Time
PLL Lock Time
QA, nQA
Output Duty Cycle
QBx, nQBx
10% to 90%
BYPASS = 0
BYPASS = 0
75
200
350
20
100
49
50
51
49
50
51
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ps
ps
ps
ps
ps
ps
ps
ms
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using Rohde & Schwarz SMA100A Signal Generator with f_REF = 30.72MHz, unless noted otherwise. V_DD and V_DDA
connected. BW[1:0] = 00.
NOTE 1: Refer to the phase noise plots.
NOTE 2: Measured from the differential input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
ICS814S208BKILF REVISION B OCTOBER 13, 2011
8
©2011 Integrated Device Technology, Inc.