ICS814S208I Datasheet, PDF (4/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
R_OUT
Output
Impedance
QLOCK
Test Conditions
QLOCK = HIGH, V_DDOL = 3.3V
QLOCK = HIGH, V_DDOL = 2.5V
QLOCK = HIGH, V_DDOL = 1.8V
QLOCK = LOW, V_DDOL = 3.3V, 2.5V, 1.8V
Minimum
Typical
2
51
51
26
32
44
22
Maximum
Units
pF
kΩ
kΩ
Ω
Ω
Ω
Ω
Function Tables
Table 3A. Output Divider N Function Table
Inputs
Operation
N_SEL
N
QB[0:7] Frequency with f_REF = 30.72MHz
0 (default)
÷5
122.88MHz, (4 * f_REF)
1
÷4
153.6MHz, (5 * f_REF)
NOTE: N_SEL is an asynchronous control.
NOTE: With f_XTAL= 30.72MHz and all control inputs in the default state, the ICS814S208I generates 30.72MHz at the QA output and
122.88MHz at the QBx outputs.
Table 3B. PLL BYPASS Function Table
Input
Operation
BYPASS
QA
QB[0:7]
0 (default)
1
f_OUT, QA = f_VCO ÷ 20
f_OUT, QA = f_REF (PLL bypass)
f_OUT, QBx = f_REF * 20 ÷ N
NOTE: BYPASS is an asynchronous control.
NOTE: In PLL bypass mode, the frequency f_REF is output at QA without frequency division. AC specifications do not apply in PLL bypass
mode.
Table 3C. PLL Reference Clock Select Function Table
Input
REF_SEL Operation
0 (default) The crystal interface is selected as reference clock
1
The REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
ICS814S208BKILF REVISION B OCTOBER 13, 2011
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©2011 Integrated Device Technology, Inc.