ICS814S208I Datasheet, PDF (17/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
Schematic Example
Figure 6 shows an example of an ICS814S208I application
schematic. In this example, the device is operated at a V_DD = V_DDOL
= 3.3V. The 12pF parallel resonant 30.72MHz crystal is used. The
load capacitance values C1 = 6.8pF and C2 = 6.8pF are
recommended for frequency accuracy. Depending on the parasitics
of the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. For this device, the
crystal load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS814S208I provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
C1
6.8pF
X1
30.₁7₂2_pM_F Hz
C2
6.8pF
VDD
R3
R4
125
125
Zo = 50
XTAL_IN
XTAL_OUT
REF_CLK
nREF_CLK
VDDOL
QLOCK
QA
nQA
R5
2.2K
BW0
BW1
nOE_B0
BY PASS
REF_SEL
U1
1
2
3
4
5
6
7
8
9
XTAL_IN
XTAL_OUT
VDD
REF_CLK
nREF_CLK
GND
VDDOL
QLOCK
10
11
12
GND
QA
nQA
VDD
VDDA
R1 10
VDD
C3
0.1u
C4
10u
N_SEL
nOE_B1
nOE_B2
nOE_A
VDD
VDD
nQB7
QB7
nQB6
QB6
GND
VDD
nQB5
36
35
34
33
32
31
30
29
28
QB5
nQB4
QB4
GND
27
26
25
QA
+
Zo_Dif f = 100 Ohm R2
100
nQA
-
LVDS Termination
VDD=3.3V
VDDOL=3.3V
QB7
Zo = 50
LVPECL Driv er
LD1
R7
R8
84
84
VDD
3.3V
BLM18BB221SN1
1
2
C6
0.1uF
Ferrite Bead C7
(U1:7)
C8
10uF 0.1uF
VDDOL
R6
Zo_Dif f = 100 Ohm 50
+
nQB7
C5
0.1uF
-
R9
50
Alternate
LVDS
Termination
3.3V
BLM18BB221SN1
1
2
(U1:3) (U1:12) (U1:18) (U1:24) (U1:30) (U1:36) VDD
C9
0.1uF
Ferrite Bead C10
C11 C12 C13 C14 C15
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C16
0.1uF
Figure 6. ICS814S208I Schematic Example
ICS814S208BKILF REVISION B OCTOBER 13, 2011
17
©2011 Integrated Device Technology, Inc.