ICS814S208I Datasheet, PDF (5/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
Table 3D. PLL Bandwidth Function Table
Inputs
Operation
BW1
BW0
PLL Bandwidth
0 (default) 0 (default) 240kHz
0 (default) 1
520kHz
1
0 (default) 1MHz
1
1
2MHz
NOTE: BW[1:0] is an asynchronous control.
NOTE: With the lowest PLL bandwidth setting (BW[1:0] = 00, 240kHz), the PLL attenuates input reference jitter with spectral components
above 240kHz. With the highest PLL bandwidth setting (BW[1:0] = 11, 2MHz), the PLL is not optimized for input reference jitter attenuation.
Table 3E. nOE_A Output Enable Function Table
Input
nOEA
Operation
0 (default) QA, nQA outputs are enabled
1
QA, nQA outputs are disabled (high-impedance)
NOTE: nOE_A is an asynchronous control.
Table 3I. QLOCK Output Function Table
Output
QLOCK
PLL Status
0
The PLL is locked to the input reference clock
1
The PLL is not locked to the input reference clock
NOTE: QLOCK supports 3.3V, 2.5V or 1.8V according to the voltage
supplied at V_DDOL. See Table 4B.
Table 3F. nOE_B0 Output Enable Function Table
Input
nOE_B0
Operation
0 (default) QB[0:3], nQB[0:3] outputs are enabled
1
QB[0:3]. nQB[0:3] outputs are disabled (high-impedance)
NOTE: nOE_B0 is an asynchronous control.
Table 3G. nOE_B1 Output Enable Function Table
Input
nOE_B1
Operation
0 (default) QB[4:5], nQB[4:5] outputs are enabled
1
QB[4:5], nQB[4:5] outputs are disabled (high-impedance)
NOTE: nOE_B1 is an asynchronous control.
Table 3H. nOE_B2 Output Enable Function Table
Input
nOE_B2
Operation
0 (default) QB[6:7], nQB[6:7] outputs are enabled
1
QB[6:7], nQB[6:7] outputs are disabled (high-impedance)
NOTE: nOE_B2 is an asynchronous control.
ICS814S208BKILF REVISION B OCTOBER 13, 2011
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©2011 Integrated Device Technology, Inc.