ICS814S208I Datasheet, PDF (3/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
2
3, 12, 18,
24, 30, 36
Name
XTAL_IN,
XTAL_OUT
V_DD
Type
Input
Power
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Core power supply pins.
4
5
6, 9, 13, 19,
25, 31, 41, 48
7
8
10, 11
14, 15
16, 17
20, 21
22, 23
26, 27
28, 29
32, 33
34, 35
REF_CLK
nREF_CLK
GND
V_DDOL
QLOCK
QA, nQA
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
QB4, nQB4
QB5, nQB5
QB6, nQB6
QB7, nQB7
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown ^{Non-inverting differential reference clock input. Differential output can accept the}
following differential input levels: LVPECL, LVDS, CML.
Pullup/ _{Inverting differential reference clock input. Differential output can accept the}
Pulldown _{following differential input levels: LVPECL, LVDS, CML.}
Power supply ground.
Output supply pin for the PLL lock output (QLOCK). Supports 3.3V, 2.5V or 1.8V.
PLL lock indication. See Table 3I for function. Supports 3.3V, 2.5V or 1.8V.
Differential clock output pair. LVDS interface levels.
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
Differential clock output pair. LVDS interface levels
37
nOE_A
Input Pulldown ^{Output enable input. See Table 3E for function.}
LVCMOS/LVTTL interface levels.
38,
nOE_B2,
39,
nOE_B1,
Input Pulldown ^{Output enable inputs. See Tables 3F-3H for function.}
45
nOE_B0
LVCMOS/LVTTL interface levels.
40
42
43, 44
N_SEL
V_DDA
BW0, BW1
Input
Power
Input
Pulldown ^{Frequency select pin. See Table 3A for function.}
LVCMOS/LVTTL interface levels.
Analog power supply.
Pulldown ^{PLL bandwidth control pins. See Table 3D for function.}
LVCMOS/LVTTL interface levels.
46
BYPASS
Input Pulldown ^{PLL bypass mode select pin. See Table 3B for function.}
LVCMOS/LVTTL interface levels.
47
REF_SEL
Input Pulldown ^{Reference select input. See Table 3C for function.}
LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS814S208BKILF REVISION B OCTOBER 13, 2011
3
©2011 Integrated Device Technology, Inc.