ICS814S208I Datasheet, PDF (13/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
3.3V LVPECL Clock Input Interface
The REF_CLK/nREF_CLK accepts LVPECL, LVDS, CML and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 2A to 2E show interface examples for the
REF_CLK/nREF_CLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
REF_CLK
nREF_CLK
LVPECL
Input
Figure 2A. REF_CLK/nREF_CLK Input Driven by an
IDT Open Collector CML Driver
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
REF_CLK
R1
100
nREF_CLK
LVPECL
Input
Figure 2B. REF_CLK/nREF_CLK Input Driven by a
Built-In Pullup CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
REF_CLK
nREF_CLK
R1
R2
84
84
LVPECL
Input
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
REF_CLK
nREF_CLK
LVPECL
Input
Figure 2C. REF_CLK/nREF_CLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. REF_CLK/nREF_CLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
Zo = 50Ω
LVDS
R5
100
Zo = 50Ω
3.3V
3.3V
R3
R4
1k
1k
C1
REF_CLK
C2
nREF_CLK
R1
R2
1k
1k
LVPECL
Input
Figure 2E. REF_CLK/nREF_CLK Input Driven by a
3.3V LVDS Driver
ICS814S208BKILF REVISION B OCTOBER 13, 2011
13
©2011 Integrated Device Technology, Inc.