ICS814S208I Datasheet, PDF (12/23 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer

ICS814S208I Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V_REF = V_DD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V_REF in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and V_DD = 3.3V, R1 and
R2 value should be adjusted to set V_REF at 1.25V. The values below
are for when both the single ended swing and V_DD are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V_IL cannot be less
than -0.3V and V_IH cannot be more than V_DD + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Power Supply Voltage Sequence Information
No power sequence restrictions apply if V_DD and V_DDA are supplied
by the same power plane and the recommended V_DDA filter is used
(see Figure 6). V_DDOL may be applied at any time before or after V_DD
and V_DDA are applied. If V_DD and V_DDA are not supplied by the same
power plane, V_DDA must be powered on before or at the same time
V_DD is applied. The V_DDOL supply voltage may be applied at any time.
ICS814S208BKILF REVISION B OCTOBER 13, 2011
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©2011 Integrated Device Technology, Inc.