92HD87 Datasheet, PDF (63/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rate
Bits
R/W
Default
1:0
RW
2h
Selects the DMic clock rate:
0h = 4.704MHz
1h = 3.528MHz
2h = 2.352MHz
3h = 1.176MHz.
Reset
POR
8.3.21. AFG (NID = 01h): DACMode
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
F8000h
Byte 1 (Bits 7:0)
780h
Field Name
Rsvd
SDMSettleDisable
SDMCoeffSel
SDMLFHalf
SDMLFDisable
InvertValid
Bits
R/W
Default
Reset
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
RW
0h
POR - S&DAFG - LR
SDM wait-to-settle disable:
1 = at mute, the SDM switches to the mute pattern immediately
0 = at mute, the SDM switches to the mute pattern after settling (can take up to
~45ms)
6
RW
0h
POR - S&DAFG - LR
DAC SDM coefficient select (stages 1, 2, 3):
1 = 1/16, 1/2, 1/4
0 = 1/16, 1/4, 1/2
5
RW
0h
POR - S&DAFG - LR
DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.
4
RW
0h
POR - S&DAFG - LR
DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feed-
back enabled.
3
RW
0h
POR - S&DAFG - LR
DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid
strobe is not inverted.
IDT CONFIDENTIAL
63
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87