92HD87 Datasheet, PDF (22/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
2.13. Analog PC-Beep
The codec does not support automatic routing of the PC_Beep pin to all outputs when the HD-Link is
in reset. Analog PC-Beep may be supported during HD-Link Reset if analog PC_Beep is manually
enabled before entering reset and the level shifters are locked. Analog PC_Beep is mixed at the port
and only ports enabled as outputs will pass PC_Beep. Analog PC_Beep (or a digital equivalent)
must not prevent passing WLP when analog PC_Beep is enabled. Analog PC_Beep, when enabled,
must not prevent other audio sources from playing (we must mix not mux.) An activity monitor will
allow the BTL amplifier (and cap-less headphone amplifiers if possible) to remain in shutdown when
the function group is in D3 until the beep pin is active and then quickly change to an active state
(within 10mS) to pass the beep tone. Beeps from ICH (from Beep.sys) can have a frequency of
about 37Hz to about 32KHz. Beep duration is programmable from 1mS to about 32 seconds. A typi-
cal beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS. Due to external XOR
gates used as mixers, the idle state may be logic 0 or logic 1.
PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced.
Analog PC_Beep is not supported in D3 Cold, or the vendor specific states D4/D5.
2.14. Digital PC-Beep
This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync
pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently
configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio
SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio
sources are disabled when digital PC_Beep is active.
It should be noted that digital PC Beep is disabled if the divider = 00h.
PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will
prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to
indicate that the part requires a clock.
2.15. Headphone Drivers
The codec implements capless headphone outputs. The Microsoft Windows Logo Program allows
up to the equivalent of 100ohms in series. However, an output level of +3dBV at the pin is required to
support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Microsoft allows device
and system manufactures to limit output voltages to address EU safety requirements. (WLP 3.09 -
please refer to the latest Windows Logo Program requirements from Microsoft.)
The capless headphone drivers are supplied with +/-2.5V derived from AVDD. Therefore, it is possi-
ble to run the headphone supply from 5V and maintain ~60mW peak output power into 32 ohm
headphones. Headphone performance will degrade if more than one port is driving a 32 ohm load.
IDT CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87